1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor memory device having a capacitor, and more particularly, to a method of manufacturing a capacitor having an improved dielectric layer between two electrodes, such as control and floating gate electrodes of a nonvolatile memory element represented by a flash memory.
2. Background Art
Referring to drawings, conventional nonvolatile memory elements and a method for manufacturing such elements will be described.
FIG. 5 shows an example of the cross sectional structure of a memory cell in a prior art flash memory, viewed from a word-line direction. In FIG. 5, 1 is a silicon substrate, 2 is a tunnel oxide film formed by thermal oxidation method, 3 is an element isolating silicon oxide film for electrically isolating between adjacent memory cells, 4 is an n-type impurity layer formed with phosphorus, arsenic, or the like on the silicon substrate 1, 5 is a floating gate electrode consisting of phosphorus-doped polycrystalline silicon, 8 is a control gate electrode consisting of phosphorus-doped polycrystalline silicon, 9 is a silicon oxide film for electrically insulating the floating gate electrode 5 and the control gate electrode 8 from adjacent memory cells, 10 is a lower-layer metal wiring, 11 is a silicon oxide film between lower-layer metal wirings 10 adjacent to each other, 12 is a upper-layer metal wiring, 13 is a silicon oxide film between the lower-layer metal wiring 10 and the upper-layer metal wiring 12, 20 is a lower silicon oxide film, 21 is a CVD-silicon nitride film, and 22 is an upper silicon oxide film.
In such a conventional flash memory, the dielectric film between the control gate electrode and the floating gate electrode for data retention characteristic is formed by three layers of the lower silicon oxide film 20, the CVD-silicon nitride film 21, and the upper silicon oxide film 22.
FIG. 6 shows the process for manufacturing a capacitor portion between the control and floating gate electrodes in a conventional example of flash memories, and shows cross sectional structures of the capacitor between the control and floating gate electrodes viewed from the bit-line direction.
In the conventional manufacturing method, first referring to FIG. 6(a), a phosphorus-doped amorphous silicon film 14 is deposited. Here, 1 is a silicon substrate, 2 is a tunnel oxide film, and 3 is an element isolating silicon oxide film. The phosphorus-doped amorphous silicon film can be formed, for example, by the CVD method using monosilane SiH4 and phosphine PH3 at 500-550xc2x0 C. The phosphorus concentration in the phosphorus-doped amorphous silicon film 14 can be controlled by changing the ratio of flow-rates of monosilane SiH4 and phosphine PH3.
Next, referring to FIG. 6(b), the phosphorus-doped amorphous silicon film 14 is processed into a desired shape by lithography and dry etching technology.
Referring now to FIG. 6(c), a lower siliconoxide film 20 is formed on the phosphorus-doped amorphous silicon film 14 by the thermal CVD method using monosilane SiH4 and dinitrogen monoxide N2O, or dichlorosilane SiH2Cl2and dinitrogen monoxide N2O at 700-900xc2x0 C. At this time, the phosphorus-doped amorphous silicon film 14 is crystallized by the thermal energy on deposition, and is converted to a floating gate electrode 5 consisting of a phosphorus-doped polycrystalline silicon.
Next, referring to FIG. 6(d), a CVD-silicon nitride film 21 is deposited on the lower silicon oxide film 20 by the thermal CVD method using monosilane SiH4 or dichlorosilane SiH2Cl2 and ammonia NH3 at 600-900xc2x0 C.
Next, referring to FIG. 6(e), an upper CVD-silicon oxide film 23 is formed on the CVD-silicon nitride film 21 by the thermal CVD method using monosilane SiH4 and dinitrogen monoxide N2O, or dichlorosilane SiH2Cl2 and dinitrogen monoxide N2O at 700-900xc2x0 C.
Next, referring to FIG. 6(f), a dense upper silicon oxide film 22 is formed by annealing the upper CVD-silicon oxide film 23 in a steam atmosphere.
Finally, referring to FIG. 6(g), a control gate electrode 8 formed of a phosphorus-doped polycrystalline silicon film is deposited on the upper silicon oxide film 22, and a capacitor between the control and floating gate electrodes is formed by lithography and dry etching process. The control gate electrode 8 can be formed by the CVD method using monosilane SiH4 and phosphine PH3 at 620xc2x0 C.
In this conventional nonvolatile memory element, the dielectric film between the control and floating gate electrodes for data retention is formed by three layers of the lower silicon oxide film 20, the CVD-silicon nitride film 21, and the upper silicon oxide film 22.
Since a three-layer structure of lower silicon oxide film/CVD-silicon nitride film/upper silicon oxide film is used in a conventional nonvolatile storage element, for example, the dielectric film between the control and floating gate electrodes of a flash memory, it was difficult to decrease the thickness of the element. Consequently, the erasing/writing speed of the flash memory was lowered.
In order to solve the above-described problems at the same time, an object of the present invention is to provide a very thin dielectric film between control and floating gate electrodes having an improved erasing/writing speed of semiconductor memory devices, in particular of flash memories or the like.
According to one aspect of the present invention, in a method of manufacturing a semiconductor memory device having a capacitor formed by arranging a dielectric film consisting of two layers of a silicon oxide film and a silicon nitride film between a silicon film and another electrode film, for forming the dielectric film, the silicon film is thermally nitrided by using NO gas to form a silicon nitride film on the silicon film, and thereafter a silicon oxide film is laminated on the silicon nitride film.
According to another aspect of the present invention, in a method of manufacturing a semiconductor memory device having a capacitor formed by arranging a dielectric film consisting of two layers of a silicon oxide film and a silicon nitride film between a silicon film and another electrode film, for forming the dielectric film, a silicon oxide film is formed on the silicon film by a CVD method, and thereafter a silicon nitride film is formed on the interface of the silicon film with the silicon oxide film by thermally nitriding the silicon film using NO gas.
According to another aspect of the present invention, in a method of manufacturing a semiconductor memory device having a capacitor formed by arranging a dielectric film consisting of two layers of a silicon oxide film and a silicon nitride film between a silicon film and another electrode film, for forming the dielectric film, a silicon oxide film is formed on the silicon film by dry oxidation method, and thereafter a silicon nitride film is formed on the interface of the silicon film with the silicon oxide film by thermally nitriding the silicon film using NO gas.
Other and further objects, features and advantages of the invention will appear more fully from the following description.